1. Field of the Invention
This invention relates generally to data communication systems and methods, and more particularly to a minimally sized data buffer that allows vector processing of simultaneous frames of overlaying data in which the frames do not have the same starting position.
2. Description of the Prior Art
When using a data communication system based on bursts (packets), the generic format of a frame consists of a preamble at the beginning of each burst. Some communication protocols additionally include data and end-of-frame. The preamble is used to signify (recognize) the start of transmission. All nodes on a network traditionally use the same preamble and the same end-of-frame. Each node, therefore, is required to decode at least the beginning of the data to identify if this message is addressed to itself. Decoding efforts importantly require a real-time computational complexity. Further, traditional data communication processes are made even more complex and time consuming due to the necessity to utilize collision detection and resolve techniques.
Further, in code division multiple access (CDMA) systems, as well as others, there are overlaying coded data streams, each having its own frame timing. In view of the foregoing, it is therefore desirable to provide a technique to minimize or even reduce communication system real-time computational complexity and hardware requirements associated with processing simultaneous frames of overlaying data in which the frames do not have the same starting position for such systems. One solution could include using a double buffer scheme, but such a scheme does not address the foregoing undesirable hardware complexity issues.
The present invention is directed to a-triple data buffer for supporting high bit rate data communication systems such as the correlator co-processor (CCP) disclosed in U.S. patent application Ser. No. 09/607,410 entitled Correlator Co-Processor For CDMA RAKE Receiver Operations, filed on Jun. 30, 2000, by Katherine G. Brown et al. The CCP is capable of receiving multiple in-phase (I) and quadrature (Q) signal samples from-multiple sources to accommodate antenna diversity wherein I and Q samples may be 6-bits or more. The I and Q samples further represent multiple overlaying channels, each of which have several multi-path elements, the aggregate data rate being possibly greater than the chip rate. The triple data buffer is a slot-aligned IQ buffer comprising three 16-chip buffers which are filled circularly. According to one embodiment, each of the 16-chip buffers contains 64 (4xc3x97 oversampled) samples of 12-bits (6 for I and 6 for Q). When one of these 16-chip buffers is being processed, the one that holds the next 16chips is used to access extra chips which are not in the current buffer. The alignment of the task""s frame determines the starting chip to be processed and then the next 15 chips are required to do the correlator vector processing which is 16 chips wide. At most, 15 more chips might be required from the next buffer. There are three 16-chip buffers, so that one buffer can be processed at any time while the next can be used to access extra chips for processing, and the third can be filled with incoming data. Frame alignment is accomplished using three levels of multiplexing. The first level selects a pair of buffers to be processed. The second level selects the sample number (0, 1, 2, 3 of the 4xc3x97 oversamples) required. The third level selects the correct chips for the alignment of the slot and is implemented using a barrel shifter to provide a smaller configuration than necessary when using brute-force multiplexing techniques.
In one aspect of the invention, an IQ data buffer is implemented to accommodate selection of IQ data bits which align to the frame/slot timing of each task.
In still another aspect of the invention, an IQ data buffer is implemented to more easily accommodate compressed mode and change of service requirements when receiving data.
In yet another aspect of the invention, an IQ data buffer is implemented that provides a simple control logic capable of rendering improved testing features over known architectures.
Still another aspect of the invention is associated with an IQ data buffer that maximizes power efficiency when executing correlations.